What happened in this episode?
Dwarkesh Patel interviews multiple Intel leaders and senior engineers about how leading-edge chip processes are developed, where scaling is headed by 2045, and what AI-driven demand means for manufacturing capacity. Intel’s Chris Auth describes the mechanics of bringing up a new node, including defect discovery via inline metrology and end-of-line tests, and argues Intel’s 10nm delays reflected overly aggressive targets and attempting innovation without mature tooling. He explains Intel’s use of maturity metrics and “phase gate” decisions to keep nodes on schedule.
The episode details technology choices Intel says it is making for 14A, including High-NA EUV as an optional path and how backside power delivery changes the lithography economics compared with TSMC’s approach. In Intel’s integration meetings, Kevin Fischer describes triaging experiments and using “hot box” prioritisation to accelerate critical wafer lots.
In Intel research labs, Jack Kavalieros discusses potential shifts in interconnect materials, including conditions under which ruthenium could supplant copper at very tight pitches, and why architectures like CFET (stacked n- and p-type devices) face aspect-ratio and integration hurdles even when simplified versions exist in R&D. In packaging, Tyler Osborn explains trade-offs between wafer-to-wafer and chip-to-wafer hybrid bonding and cites published reliability data for sub-micron pitches.
Intel CTO Pushkar Ranade argues that equipment supply — not just EUV — constrains how fast output can expand, estimating a possible ~2x increase rather than 10x under current conditions. He also predicts that hyperscaler demand could effectively consume entire fabs, and claims Intel is working with Elon Musk on a proposed “Terafab”.
