FPGA Energy Efficiency Not as Superior to ASICs as Commonly Assumed

What was said

"If you run a chip much slower and you only clock it once every 1,000 clock cycles or something, you will have 1,000 times fewer transitions. It'll be about 1,000 times less energy consumption, but not a substantial advantage in energy efficiency."

Reiner Pope, CEO of Maddx, challenged the common assumption that FPGAs achieve superior energy efficiency through slower clock cycles. While FPGAs do consume less total energy when clocked slowly, Pope explained that this doesn't translate to efficiency gains because chips consume energy primarily when toggling bits, not while idle. This technical insight contradicts conventional wisdom in hardware design circles.